Reading

• Day 1
  • Recommended:
    1. Stephen M. Trimberger. Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology. In Proceedings of the IEEE, Volume 103, Number 3, p. 318--331, March 2015.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapters 1, 2, 6, In Zynq Book.
  • Supplemental:
    1. Xilinx Zynq Overview
• Day 2
  • Recommended:
    1. Donald E. Knuth. An empirical study of FORTRAN programs. In Software Practice and Experience, Volume 1, Number 2, pages 105--133, August, 1971. See Canvas site.
    2. Gene Amdahl. Validity of the single processor approach to achieving large scale computing capabilities. In Proceedings of the Spring Joint Computer Conference (AFIPS), Pages 483-485, 1967.
  • Supplemental:
    1. TBD
• Day 3
  • Recommended:
    1. Ulrich Drepper, What Every Programmer Should Know about the Memory, 2007 Chapters 1--3.2
  • Supplemental:
    1. Brent Keeth and Jacob Baker, DRAM Circuit Design: A Tutorial, IEEE Press, 2001, pp. 108--116.
    2. Ashok K. Sharma, Semiconductor Memories, IEEE Press, 1997, pp. 230--248.
• Day 4
  • Recommended:
    1. André DeHon. Chapter 5, In Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Elsevier, 2008. See Canvas site.
  • Supplemental:
    1. TBD
• Day 5
  • Recommended:
    1. Gilles Kahn. The Semantics of a Simple Language for Parallel Processing. In Information Processing, pages 471--475, 1974.
  • Supplemental:
    1. Edward A. Lee and David G. Messerschmitt. Synchronous Data Flow. In Proceedings of the IEEE, Volume 75, Number 9, pp. 1235--1245, September, 1987.
    2. André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, and John Wawrzynek. Stream Computations Organized for Reconfigurable Execution, In Microprocessors and Microsystems, Volume 30, Number 6, Pages 334--354, September 2006. See Canvas site.
    3. Edward A. Lee. and Albert Sangiovanni-Vincintelli. A Framework for Comparing Models of Computation. In IEEE Transactions on Computer-Aided Design, Volume 17, Number 12, pp. 1217--1229, December, 1998.
• Day 6
  • Recommended:
    1. W. Daniel Hillis and Guy L. Steele Data Parallel Algorithms. In CACM 29(12)1170--1183, 1986.
    2. John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, and Nelson Morgan. Spert-II: A Vector Microprocessor System, IEEE Computer, 1996.
  • Supplemental:
    1. R.M. Russell, The CRAY-1 Computer System. In CACM 21(31)63--72, 1978.
• Day 7
  • Recommended:
    1. Greg Snider, Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware, FPGA, 2002. [also here]
       Note: Background section is most relevant for this day; the rest may be a bit early, but becomes more relevant over the next few lectures.
  • Supplemental:
    1. TBD
• Day 8
  • Recommended:
    1. André DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41--49, April 2000.
  • Supplemental:
    1. Timothy J. Callahan, John R. Hauser and John Wawrzynek The GARP Architecture and C Compiler. IEEE Computer, vol. 33, no. 4, pp. 62-69, Apr 2000.
• Day 9
  • Recommended:
    1. Timothy J. Callahan and André DeHon. Chapter 7. In Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Elsevier, 2008. See Canvas site.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapters 14, 15, In Zynq Book.
  • Supplemental:
    1. HLSynth TRCAD 2011
• Day 10
  • Recommended:
    1. UltraFast High-Level Productivity Design Methodology Guide (UG1197) most of Chapter 4, C-based IP-development, p. 35--57.
  • Supplemental:
    1. Vivado Design Suite Users Guide: High Level Synthesis (UG902), Optimizing the Design, pp. 131--187. (some overlap with above, so read above and skim redundant sections.)
    2. Zhipeng Zhao and James C. Hoe. Using Vivado-HLS for Structural Design: a NoC Case Study, CMU 2017.
• Day 11
  • Recommended:
    1. Haiqian Yu and Miriam Leeser. Automatic Sliding Window Operation Optimization for FPGA-Based Computing Boards. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines, pp. 76--88, 2006.
    2. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapter 9.3, 10 In Zynq Book.
  • Supplemental:
    1. Louise H. Crockett, Ross A. Elliot, Martin A. Enderwitz, and Robert W. Stewart. Chapter 19 In Zynq Book.
    2. Eric S. Chung, James C. Hoe and Ken Mai. CoRAM: an in-fabric memory architecture for FPGA-based computing, in Proceedings of the International Symposium on Field-Programmable Gate Arrays, pp. 97--106, 2011.
    3. Andrew S. Huang and John P. Shen. ``A Limit Study of Local Memory Requirements Using Value Reuse Profiles'', in Proceedings of MICRO-28, pp. 71--81, December, 1995.
    4. Edward A. Lee. The Problem with Threads. In IEEE Computer, Volume 39, Issue 5, pp. 33--42, 2006.
• Day 12
  • Recommended:
    1. Ulrich Drepper, What Every Programmer Should Know about the Memory, 2007 Chapters 1--3.2
  • Supplemental:
    1. TBD
• Day 13
  • Recommended:
    1. Joseph A. Fisher. Very Long Instruction Word Architectures and the ELI-512. In Proceedings of the International Symposium on Computer Architecture, 1983.
  • Supplemental:
    1. Joseph A. Fisher. ``Retrospective: Very Long Instruction Word Architectures and the ELI-512,'' In 25 Years of the International Symposia on Computer Architecture: Selected Papers, pp. 34--36, 1998.
    2. PICO (Program In, Chip Out): Automatically Designing Custom Computers. In IEEE Computer, vol. 35, no. 9, pp. 39-47, September 2002.
• Day 14
  • Recommended:
    1. Monica Lam. Software Pipelining: An Effective Scheduling Technique for VLIW Machines. In Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation, pp. 318--328, 1988.
  • Supplemental:
    1. TBD
• Day 15
  • Recommended:
    1. None
• Day 16
  • Recommended:
    1. See project handout.
  • Supplemental:
    1. TBD
• Day 17
  • Recommended:
    1. Udit Dhawan and André DeHon. Area-Efficient Near-Associative Memories on FPGAs. In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Number 4, DOI: 10.1145/2629471, January, 2015.
  • Supplemental:
    1. Adam Kirsch and Michael Mitzenmacher. 2010. The power of one move: Hashing schemes for hardware. IEEE/ACM Trans. Networking 18, 6 (2010), 1752–1765.
• Day 18
  N/A
• Day 19
  • Recommended:
    1. Matteo Frigo and Steven G. Johnson, The Design and Implementation of FFTW3. In Proceedings of the IEEE, vol. 93, no. 2, pp. 216--231, 2005.
  • Supplemental:
    1. R. Clint Whaley, Antoine Petitet, and Jack Dongarra. Automated Empirical Optimization of Software and the ATLAS Project. In Parallel Computing, Volume 27, pp. 3--35, February, 2001.
• Day 20
  • Recommended:
    1. Edin Kadric, David Lakata, André DeHon, Impact of Parallelism and Memory Architecture on FPGA Communication Energy. In ACM Trans. on Reconfigurable Technology and Systems, 2016.
  • Supplemental:
    1. Rajesh Kumar and K. Bernstein. Scaling, power, and the future of CMOS. In Technical Digest of the IEEE International Electron Device Meeting, December 2005, pp. 7--15.
    2. Hadi Esmaeilzadeh, Emily Blem, Rene St. Amant, Karthikeyan Sankaralingam, and Doug Burger Dark silicon and the end of multicore scaling'' in Proceedings of the International Symposium on Computer Architecture, 2011, pp. 365--376.
    3. Borivoje Nikolic. Design in the Power-limited Scaling Regime. In IEEE Transaction on Electron Devices, Volume 55, Number 1, pp. 71--83, 2008.
    4. David J. Frank. ``Power-constrained CMOS Scaling Limits,'' IBM Journal of Research and Development, Volume 46, Number 2/3, March/May, 2002. See Canvas site.
    5. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester. ``Ultralow-voltage, minimum-energy CMOS,'' IBM Journal of Research and Development, Volume 50, Number 4/5, pp. 471--490, July/September 2006.
    6. David Bol, Renaud Ambroise, Denis Flandre, and Jean-Didier Legat. ``Interests and Limitations of Technology Scaling for Subthreshold Logic,'' In IEEE Trans. on VLSI Systems, Vol. 17, No. 10, pp. 1508--1519, 2009.
    7. Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, ``Low-Power CMOS Digital Design,'' in IEEE Journal of Solid State Circuits, 1992, Vol. 27, No. 4, pp. 473--484.
    8. Richard P. Feynman. Feynman Lectures on Computation. Westview Press, 1999. Chapter 5: Reversible Computation and the Thermodynamics of Computation, pp. 137--184.
• Day 21
  • Recommended:
    1. TBD
  • Supplemental:
    1. B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20(12):1469--1479, 1971. (n.b. This is the classic paper showing empirical evidence for Rent's Rule.)
    2. Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P. Jouppi. CACTI 6.0: A Tool to Model Large Caches. HPL-2009-85, HP Labs, Palo Alto, CA, 2009.
    3. Special issue of IEEE Solid-State Circuits Magazine on Rent, including original memo
• Day 22
  • Recommended:
    1. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A. Edwards, and Edward A. Lee. Predictable programming on a precision timed architecture, In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pp. 137--146, 2008.
  • Supplemental:
    1. TBD
• Day 23
  • Recommended:
    1. André DeHon. Chapter 37: Defect and Fault Tolerance. In Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Elsevier, 2008. See Canvas site.
  • Supplemental:
    1. Avinash Sodani, Roger Gramunt, Jesus Corbal, Ho-Seop Kim, Krishna Vinod, Sundaram Chinthamani, Steven Hutsell, Rajat Agarwal, and Yen-Chen Liu. Knights Landing: Second-Generation Intel Xeon Phi Product, IEEE Micro, volume 36, issue 2, pp. 34--46 ,March 2016.
    2. David Patterson, Garth Gibson, and Randy Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID). In Proceedings of the ACM SIGMOD Conference, p. 109--116, June 1988.
    3. W. Bruce Culbertson and Rick Amerson and Richard Carter and Phil Kuekes and Greg Snider, Defect Tolerance on the TERAMAC Custom Computer. In International Symposium on Field-Programmable Custom Computing Machines, pp. 116--123, 1997.
• Day 26
  • Recommended:
    1. Robert Walker and Samit Chaudhuri. Introduction to the Scheduling Problem, IEEE Design and Test of Computers, Volume 12, Issue 2, pp. 60--69, 1995.
  • Supplemental:
    1. The Synchronous Data Flow Pogramming Language LUSTRE. In Proceedings of the IEEE, 1991.
    2. The Synchronous Approach to Reactive and Real-Time Systems. In Proceedings of the IEEE, 1991.
• Day 27
  • Recommended:
    1. William J. Dally and Brian Towles, Route Packets, Not Wires: On-Chip Interconnection Networks. In Proceedings of the Design Automation Conference, pp. 684-689, 2001.
  • Supplemental:
    1. Nachiket Kapre and Jan Gray, Hoplite: Building austere overlay NoCs for FPGAs. In International Conference on Field-Programmable Logic and Applications, 2015.
    2. Nachiket Kapre, Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs. In International Symposium on Field-Programmable Custom Computing Machines, 2016.
    3. Charles Seitz, Let's Route Packets Instead of Wires. In Proceedings of the 6th MIT Conference on Advanced Research in VLSI, pp. 133--137, 1990. [online link?]
    4. Jose Duato, Sudhakar Yalamanchili, and Lionel Ni. Interconnection Networks, Morgan Kaufmann, 2002.
    5. William Dally and Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.