MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources

Article by Ethan Mirsky and André DeHon published in Proceedings of the 1996 IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96), pp. 157--166, April, 1996.

MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution. Device resources are allocated to controlling and describing the computation on a per task basis. Application-specific regularity allows us to compress the resources allocated to instruction control and distribution, in many situations yielding more resources for datapaths and computations. The adaptability is made possible by a multi-level configuration scheme, a unified configurable network supporting both datapaths and instruction distribution, and a coarse-grained building block which can serve as an instruction store, a memory element, or a computational element. In a 0.5um CMOS process, the 8-bit functional unit at the heart of the MATRIX architecture has a footprint of roughly 1.5mm x 1.2mm, making single dies with over a hundred of function units practical today. At this process point, 100MHz operation is easily achievable, allowing MATRIX components to deliver on the order of 10 Gop/s (8-bit ops).