The MATRIX chip represents a novel, reconfigurable computing architecture which supports configurable instruction distribution. Device resources are allocated to controlling and describing the computation on a per-task basis. Application-specific regularity and parallelism allows us to compress the resources allocated to instruction control and distribution in many situations, yielding more resources for datapaths and computations. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). A modest 0.6um CMOS university prototype running at 50MHz delivers 1.8 Gop/s (8-bit ops) in 130 sq. mm.