ESE535: Electronic Design Automation

Spring 2013

Working schedule subject to refinement.
Check http://www.seas.upenn.edu/~ese535/spring2013/spring2013.html for updates.

Date Topic Slides Reading Due Assign
1/9 Introduction, Motivation, Overview ppt, pdf none
1/14 Covering ppt, pdf Devadas p190--198
1/16Scheduled Operator Sharing ppt, pdf HL Synth D&T 1994 Assign 1
1/21MLK Holiday (no class)
1/23 Scheduling I (formulation, List Scheduling) ppt, pdf Scheduling Intro D&T 1995
1/28 Scheduling II (force-directed, Branch-and-Bound) ppt, pdf Component-Specific FPGA 2012
associated with project not lecture
Assign 1 Assign 2
1/30 Partitioning I (formulation and KLFM) ppt, pdf KLFM DAC 1982
2/4 Clustering ppt, pdf flowmap TRCAD 1994 Assign 2a
2/6 Partitioning II (spectral, maxflow, replication) ppt, pdf Hall Mngmt Sci 1970
2/11 Placement I (formulation and constructive) ppt, pdf Part Place ISPD 1997 Assign 2b Assign 3, 4
2/13 FPGA (no class)
2/15Drop Day
2/18 Placement II (simulated annealing) ppt, pdf SA Science 1983
2/20 Routing I (variants, formulation, channel routing, over-the-cell) ppt, pdf Left Edge DAC 1971 Assign 3
2/25 Routing II (Pathfinder congestion negotiation, FPGA routing) ppt, pdf Pathfinder FPGA 1995
2/27 Dataflow Compute Models ppt, pdf SDF Proc. IEEE 1987 Assign 4
3/4Spring Break (no class)
3/6 Spring Break (no class)
3/11 High-level Synthesis I (C-to-dataflow graph) ppt, pdf Hauck+DeHon, Ch. 7 Assign 5
3/13 High-level Syntehsis II: Dataflow Subgraph Sharing ppt, pdf HLSynth TRCAD 2011
Pattern FPGA2008
3/18 Architecture Synthesis ppt, pdf PICO Computer2002 Assign 5a
3/20 Satisfiability (SAT) solvers ppt, pdf Chaff DAC2001
3/25 Two-level Logic ppt, pdf Devadas p59--91 Assign 5b Assign 6--7
3/27 FSM Encoding (Sequential logic) ppt, pdf Exact Encode TRCAD 1991
3/29Withdraw Day
4/1 FSM Equivalence Checking ppt, pdf seq. verify TRCAD 1988 Assign 6
4/3 Multi-level Logic ppt, pdf Devadas p151--184
4/8 Static Timing Analysis ppt, pdf Devadas p225--256 Assign 7m1
4/10 Statistical Static Timing Analysis ppt, pdf SSTA DAC 2002
4/15 Retiming ppt, pdf Retime Caltech VLSI 1983 Assign 7m2
4/17 Simultaneous Retiming and Covering ppt, pdf Cover+Retime DAC 1996
4/22 Processor Verification ppt, pdf Processor Verify CAV 1994 Assign 7 Assign 8
5/07 During Finals (no class) Assign 8


ESE535: Electronic Design Automation